Table of Contents

Agnus Amiga Custom Chip

Agnus handles the following on the Amiga:

Blitter

Amiga Agnus Blitter

DMA

Examples

Enabling copper, bitplane rendering, and blitter

You need to control DMACON: http://coppershade.org/articles/Code/Reference/DMACON/

snippet.asm
DMACON.COPPER   EQU %0000000010000000
DMACON.BITPLANE EQU %0000000100000000
DMACON.BLITTER  EQU %0000000001000000
 
  MOVE.W #%1000000111000000,DMACON
  MOVE.W #%0000000000111111,DMACON
snippet.c
#include <hardware/dmabits.h>
 
// enable
custom.dmacon = DMAF_SETCLR | DMAF_COPPER | DMAF_RASTER | DMAF_BLITTER;
 
// disable
custom.dmacon = DMAF_AUDIO | DMAF_DISK | DMAF_SPRITE;

Copper (co-processor)

Amiga Agnus Copper Co-Processor

Setting up a display

There seems to be a real common pattern of setting:

    The normal NTSC DIWSTRT is ($2C81).
    The normal NTSC DIWSTOP is ($F4C1).

    The normal PAL DIWSTRT is ($2C81).
    The normal PAL DIWSTOP is ($2CC1).

Examples

Display Setup

PAL Lowres, 5 bitplanes

snippet.asm
BPLCON0.COLOR EQU %0000001000000000
BPLCON0.BPU_5 EQU %0101000000000000
 
  MOVE.W #(BPLCON0.COLOR|BPLCON0.BPU_5),BPLCON0
  MOVE.W #0,BPLCON1
  MOVE.W #0,BPL1MOD
  MOVE.W #0,BPL2MOD
  MOVE.W #$2C21,DIWSTRT
  MOVE.W #$2CC1,DIWSTOP
  ;MOVE.W #$38C1,DIWSTOP
  MOVE.W #$0038,DDFSTRT
  MOVE.W #$00D0,DDFSTOP

Waiting for a vertical blank on PAL

The code that is everywhere is:

snippet.asm
WaitVBL:
  MOVE.L $DFF004,D0
  AND.L #$1FF00,D0
  CMP.L #300<<8,D0
  BNE.B WaitVBL
snippet.c
void WaitVBL() {
  while ((custom.vposr & 0x1FF00) != (300 << 8)) {}
}

This works because you're reading both `VPOSR` and `VHPOSR` in one operation into D0:

VPOSR                            VHPOSR
| | | | | | | | | | | | | | | | | V8 | V7 | V6 | V5 | V4 | V3 | V2 | V1 | V0 | h | h | h | h | h | h | h | h |

AND.L #$1FF000,D0 masks out the h and keeps the V#. CMP.L #Height<<8 shifts height over 8 bits to the left, then compares the value to the results of the AND.

If you run this on an NTSC Amiga it will lock up!

There's also http://ada.untergrund.net/?p=boardthread&id=31&page=last


Reference

DMACON flags

These are bits that are ORed together. Remember, the more you enable, the more contention there is for RAM and CPU timing, especially on even clock cycles.

You can also read some blitter-related flags on DMACONR: